F E D C B A 9 8 7 6 5 4 3 2 1 0 +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ | | | | | O| D| I| T| S| Z| | A| | P| | C| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ C - Carry Flag : Set if Carry Out Z - Zero Flag : Set if Zero Result S - Sign Flag : Set if Negative Result O - Overflow Flag : Set if Carry In != Carry Out D - Direction Flag : If Set then Up; If Clear then Down P - Parity Flag : Set if Parity Even; Clear if Parity Odd A - Auxiliary Carry : Used for BCD arithmetic I - Interrupt : If Set Enable Interrupts; If Clear Disable Interrupts T - Trap : If Set CPU executes single instruction followed by INT 01
sub al, 0dh ; subtract ASCII code for CR from AL je Done ; if equal branch to DoneHowever, the subtraction operation above is destructive in that it overwrites the operand in the AL register. Hence the CMP insturction which is a non-destructive subtraction.
CMP destination, source subtracts source from destination sets flags does not alter destinationIn this case, to compare the contents of the AL register with 0dh
cmp al, 0dh ; compare AL with ASCII CR je Done ; if equal branch to done
CF and ZF Flag Configurations for Unsigned Comparisons destination > (above) source : CF = 0 ZF = 0 destination = (equal) source : CF = 0 ZF = 1 destination < (below) source : CF = 1 ZF = 0 je jump if equal ZF = 1 same as jz jne jump if not equal ZF = 0 same as jnz ja jump if above CF = 0 and ZF = 0 same as jnbe jae jump if above or equal CF = 0 same as jnb jb jump if below CF = 1 same as jnae jbe jump if below or equal CF = 1 or ZF = 1 same as jna
OF and SF Flags Configurations for Signed Comparisons if destination > source then a. no overflow if OF = 0 then SF = 0 b. on overflow if OF = 1 then SF = 1 if destination < source then a. no overflow if OF = 0 then SF = 1 b. on overflow if OF = 1 then SF = 0 jg jump if greater than (ZF = 0) and (SF = OF) same as jnle jge jump if greater than or equal SF = OF same as jnl jl jump if less than SF != OF same as jnge jle jump if less than or equal (ZF = 1) or (SF != OF) same as jngNote. The testing of equality and non-equality is the same for both signed and unsigned integers.
jo jump on overflow OF = 1 jno jump on no overflow OF = 0 jc jump on carry CF = 1 jnc jump on no carry CF = 0 js jump on sign negative SF = 1 jns jump on sign positive SF = 0 jpe jump on parity even (same as jp) PF = 1 jpo jump on parity odd (same as jnp) PF = 0 jcxz jump on CX register = 0 CX = 0000h
loop dest decrement CX and jump to dest if CX != 0 loope dest loop on equal decrement CX and jump to dest if CX != 0 and ZF = 1 loopne dest loop on not equal decrement CX and jump to dest if CX != 0 and ZF = 0A bottom test loop is easily implemented using the CX register as the loop counter. Use the jcxz instruction before the loop to insure that CX > 0
mov cx, n ; initialize CX jcxz EndLoop1 ; make sure CX > 0 Loop1: ; loop body begins here loop Loop1 EndLoop1: ; 1st instruction after Loop1In addition to terminating a loop if CX = 0, the loope and loopne instructions allow a loop to be terminated if the Zero Flag is set (or cleared). For example a loop ending with
cmp ax, bx loopne Loop1 EndLoop1:would terminate if CX equal to 0 or AX equal to BX.
Conditional and unconditional branching on the ARC is similar to the Intel 80x86 except simpler! There is only one unconditional branch instruction (ba or branch always) which adds a signed displacement value contained in the current instruction to the %pc register (note that the %pc register, unlike the Intel 80x86 ip register contains the address of the current instruction.
Like the Intel 80x86 the ARC does conditional branching by testing condition codes set/cleared by the execution of previous instructions. However unlike the Intel 80x86 only special instructions (those terminating in "cc") can affect the condition codes. This allows programs to set/clear the condition code, execute other instructions, then test the condition code (and branch) from a later point in the instruction stream.
Like the Intel 80x86 the ARC has four condition codes: N (negative), Z (zero), C (carry out) and V (overflow) which allow both signed (e.g. bgu - branch on greater unsigned) and signed (e.g. bg - branch on greater) comparisons - inplemented the same way as on the Intel 80x86.
However, unlike the Intel 80x86 the ARC does have any native loop instructions. Counting loops must be implemented using conditional branch instructions
Conditional branching on the PDP-8 is fundamentally different. Instead of having condition codes (ARC) or flags (Intel 80x86) which are set/cleared depending on a previous operation, the PDP-8 tests the current value of the Accumulator or Link bit executing a skip instruction if the test is true.
The accumulator can be tested for zero/non-zero (i.e. all bits are zero or not) and/or negative/positive (bit 0, the sign bit, is set/cleared). There is no test for signed overflow. Carry out (unsigned overflow) is done by testing the Link bit.
Since only conditional skip instructions are supported (e.g. sma or spa, sza or snz, snl or szl) the only way to implement a conditional branch jump instruction is to reverse the logic and pair the conditonal skip instruction with a jmp instruction. For example a "goto L0 if accumulator is positive" instruction would be implemented as ...
sma / if AC >= 0 jmp LO / goto L0
The PDP-8 does have a native "loop" instruction the iac jmp pair which is a count up loop starting at a negative number.